SPIFISEL=SYSCLK
SPIFI Clock Selection register
| SPIFIDIV | Selects the divide value for creating the SPIFI clock from the selected clock source. 0 = The divider is turned off., no clock will be provided to the SPIFI. 1 = The input clock is divided by 1 to produce the SPIFI clock. 2 = The input clock is divided by 2 to produce the SPIFI clock. 3 = The input clock is divided by 3 to produce the SPIFI clock. … 31 = The input clock is divided by 31 to produce the SPIFI clock. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| SPIFISEL | Selects the input clock for the USB clock divider. 0 (SYSCLK): Sysclk is used as the input to the SPIFI clock divider. 1 (MAINPLLOUT): The output of the Main PLL is used as the input to the SPIFI clock divider. 2 (ALTPLLOUT): The output of the Alt PLL is used as the input to the SPIFI clock divider. 3 (RESERVED): Reserved, this setting should not be used. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |